Conventionally, there is known a solid-state imaging apparatus in which the carriers of a photoelectric conversion element are transferred by a transfer MOS transistor to a floating diffusion region, converted to a voltage, and then read out. In such a solid-state imaging apparatus as described above, electrons from the channel portion of the transfer MOS transistor flow into the photoelectric conversion element in some cases during an accumulating period at the photoelectric conversion element, thus changing into a dark current. On the other hand, Japanese Patent Application Laid-Open No. 2001-245216 (hereinafter referred to as Patent Document 1) discloses a configuration in which a dark current is suppressed by setting a signal level applied to the control electrode of a transfer MOS transistor in an off state lower than a signal level applied to the control electrode of another MOS transistor in an off state.
In addition, Japanese Patent Application Laid-Open No. 2004-111590 (hereinafter referred to as Patent Document 2) discloses a configuration in which a carrier accumulating portion arranged in association with each photoelectric conversion element is provided in a pixel, thereby performing electronic shutter operation. A storage pulse is input to the gate electrode of the carrier accumulating portion. As this storage pulse, an active pulse is supplied immediately before an accumulating period or an inactive pulse is supplied during the accumulating period. After that, the carrier accumulating portion is cleared for all pixels at a time before the signal carriers of each photoelectric conversion element are transferred to the carrier accumulating portion. Specifically, a readout selection transistor is turned on at the end of an accumulating period at the photoelectric conversion element before a frame shift pulse (storage pulse) is activated. Thus, unnecessary carriers accumulated in the carrier accumulating portion are transferred to a floating diffusion region to reset the photoelectric conversion element.
In Patent Document 2, satisfactory consideration has not been given to the amplitude of a pulse to be input to the gate electrode of the carrier accumulating portion, particularly to a voltage to be supplied during an accumulating period.
In addition, there is the possibility that a dark current also mixes into the carrier accumulating portion during the carrier-holding period of the carrier accumulating portion. The dark current is generated at a boundary between a carrier-accumulating semiconductor region of the carrier accumulating portion and a surface oxide film, and mixes into carriers retained in the carrier holding portion. This problem has a particularly significant influence if the impurity concentration of the semiconductor region of the carrier holding portion is increased to a certain degree, in order to increase the amount of carriers retained in the carrier holding portion. In addition, as described in Patent Document 1, it is important to suppress a dark current in a channel portion underneath a transfer electrode. Conventionally, no consideration has been given, however, to a relationship between a voltage supplied during the non-conducting period of a transfer portion and a voltage supplied to the gate electrode of the carrier holding portion during the accumulating period of the carrier holding portion. Maintaining the withstand voltage of a MOS transistor is a critical issue particularly when operating the solid-state imaging apparatus at a low voltage.
In view of the above-described problems, it is an object of the present invention to achieve both the reduction of a dark current mixing into a carrier holding portion and the maintenance of the withstand voltage of a transfer portion.